1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device having a capacitive element, specifically to a technology to improve characteristics of a dielectric film of the capacitive element.
2. Description of the Related Art
In a method to form a capacitive element in a semiconductor device, a dielectric film and an upper electrode are formed on a lower electrode having the same structure as a gate electrode. The lower electrode in this manufacturing method often takes a polycide structure, i.e., stacked layers of a polycrystalline silicon film and a tungsten silicide film.
The dielectric film made of an insulating material is formed on the lower electrode and the upper electrode made of a polycrystalline silicon film is formed on the dielectric film. The method has a merit that the lower electrode can be formed simultaneously with the gate electrode, since the lower electrode has the same structure as the gate electrode. The manufacturing method is hereinafter described in detail with respect to FIGS. 6–9.
A polycrystalline silicon film 12 is formed on a silicon oxide film 11 which is formed on a semiconductor substrate (not shown) by LOCOS (Local Oxidation of Silicon), as shown in FIG. 6. Explanations on a method to form the silicon oxide film by LOCOS is omitted since it is well known to those skilled in the art.
The resistivity of the polycrystalline silicon film 12 needs to be reduced in order to use it as an electrode. The resistivity of the polycrystalline silicon film may be reduced by any of available methods, including doping it with impurities during formation of the polycrystalline silicon film and doping it with impurities by thermal diffusion or ion implantation after forming the polycrystalline silicon film.
After that, a tungsten silicide film 13 and a silicon oxide film 14 which will be used as a hard mask in patterning the lower electrode are formed on the polycrystalline silicon film 12.
The silicon oxide film 14 to be used as the hard mask is etched using a patterned photoresist film (not shown) as a mask, and then the photoresist film is removed. The tungsten silicide film 13 and the polycrystalline silicon film 12 are etched using the patterned silicon oxide film 14 as the hard mask. The lower electrode is hereby formed.
After that, source and drain regions are formed by implanting impurity ions into regions adjacent the gate electrode formed simultaneously with the lower electrode, followed by thermal diffusion of the impurity ions. A silicon oxide film 15 which makes a sidewall is formed on each side surface of the lower electrode to make the source drain regions LDD (Lightly Doped Drain) structure, as shown in FIG. 7. The tungsten silicide film 13 is crystallized due to a heat treatment to form the source drain regions, as depicted as 13A in FIG. 7.
Next, an opening is formed by plasma etching in the silicon oxide film 14 used as the hard mask to provide a region for contact between the tungsten silicide film 13 and the dielectric film to be formed, as shown in FIG. 8. Part of the tungsten silicide film 13A in the opening undergoes a phase transformation from crystalline to amorphous in this process due to damage done by the plasma etching, as depicted as 13B in FIG. 8.
After forming the dielectric film, the polycrystalline silicon film 19 to make the upper electrode of the capacitive element is formed on the dielectric film, as shown in FIG. 9. The resistivity of the polycrystalline silicon film 19 is also reduced by the method described above.
The most common material for the dielectric film is a silicon nitride film. The dielectric film may be made of a silicon nitride film and a silicon oxide film formed under the silicon nitride film. Or, it may be made of a silicon nitride film and a silicon oxide film formed on the silicon nitride film by oxidizing a top portion of the silicon nitride film. The dielectric film is made of stacked layers of a silicon oxide film 16, a silicon nitride film 17 and a silicon oxide film 18 in this embodiment.
Patterning a photoresist film (not shown) and etching the polycrystalline silicon film 19 and the dielectric film complete the formation of the capacitive element. Further details may be found in Japanese Patent No. 2705476
There is a problem in the manufacturing method described above. The breakdown voltage of the dielectric film is not high enough. Consequently the capacitive element can not be used in a semiconductor device operating at high voltage and the capacitive element can not store a large quantity of electric charge.